1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method of forming low resistance contact structures in vias which are configured between interconnects arranged on two separate topological levels.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, often called interconnect lines (i.e., interconnects). Interconnects are patterned from conductive layers formed on or above the surface of a silicon substrate. One or more conductive layers may be patterned to form one or more levels of interconnects vertically spaced from each other by one or more interlevel dielectric layers. Dielectric-spaced interconnect levels allow formations of densely patterned devices on relatively small surface areas. Interconnects on different levels are commonly coupled electrically using contact structures formed in vias (i.e., holes etched through interlevel dielectric layers separating the interconnects).
The operating speed of an integrated circuit is limited by transistor switching times and signal propagation delays associated with signal lines along one or more critical signal paths through the circuit. A signal line formed between input/output terminals of an integrated circuit comprises interconnects arranged on one or more levels, connected by contact structures (i.e., contacts) disposed between the interconnect levels. Resistance of each signal line is equal to the sum of the resistance values of the interconnect lines and the contacts making up the signal line. As feature sizes shrink, transistor switching times typically decrease while signal propagation delays of signal lines typically increase. In fact, the maximum operating speeds of integrated circuits with submicron feature sizes are typically limited by signal propagation delays associated with signal lines. Thus if the maximum operating speeds of integrated circuits are to increase as device dimensions shrink, the resistance values associated with interconnect lines and contacts must also be reduced to achieve the desired speed.
Following the formation and patterning of an interconnect level, an interlevel dielectric layer is deposited over the interconnect level. Prior to the formation and patterning of a subsequent interconnect level, vias are etched through the interlevel dielectric layer in locations where interconnects on different interconnect levels are to be electrically coupled. Conductive material used to form a layer of interconnects is typically deposited on or above the surface of a silicon substrate by sputter deposition. As long as sputter deposition can adequately fill the vias, special via-filling procedures are not required. However, in order to increase layout densities, advanced submicron fabrication technologies typically require a via-filling operation be incorporated into the process sequence prior to the deposition and patterning of subsequent interconnect levels. Metal via plugs thus formed in via openings constitute contact structures arranged in electrical contact between interconnects on different levels. The via openings are formed through interconnect dielectric layers which, when filled with metallic via plugs, comprise a contact structure.
A layer of photoresist is typically formed on the surface of an interlevel dielectric layer and patterned to define via locations. During via etch, organic material derived from the photoresist layer forms what is believed to be a polymer layer on the exposed upper surfaces of the interconnects at the bottoms of the vias. After the vias have been formed but before the via plug material is deposited, portions of the upper surfaces of interconnects located at the bottoms of the vias are exposed to oxygen in the ambient. A native oxide layer may thus be formed on the exposed upper surfaces of the interconnects at the bottoms of the vias in combination with the polymer layer. Oxide and/or carbon-based polymer materials, both poor conductors of electricity, result in an increase in the electrical resistance of contact structures subsequently formed in the vias. In order to form low resistance contact structures, it is necessary to remove any and all etch byproduct polymer and oxide layers from exposed interconnect surfaces at the bottoms of the vias prior to forming contact structures within the vias.
Resistance values of metal-to-metal contact structures formed using conventional processes may vary considerably. Highly resistive contact structures in critical signal paths of an integrated circuit will deleteriously reduce the maximum operating speed of that circuit. It would thus be advantageous to have a method of forming low resistance contact structures in vias between interconnect lines arranged on different interconnect levels.